Implementation and modeling of parametrizable high-speed Reed Solomon decoders on FPGAs

verfasst von

A. Flocke, H. Blume, T. G. Noll

Abstract

One of the most important error correction codes in digital signal processing is the Reed Solomon code. A lot of VLSI implementations have been described in literature. This paper introduces a highly parametrizable RS-decoder for FPGAs. By implementing resource-sharing and by using a fully pipelined multiplier/adder-unit in GF(2m) it was possible to achieve high throughput rates up to 1.3Gbit/s on a standard FPGA, while using only an attractive small amount of logical elements (LE). The implementation, written in a hardware description language (HDL), is based on an inversionless Berlekamp Algorithm (iBA), whose structure leads to a chain of identical processing elements (PE). The critical path of one PE runs only through one adder and one multiplier. A detailed description of a resource-sharing methodology for this Berlekamp Algorithm and the achievable gain are presented in this paper.p/p styleCombining double low line"line-height: 20px;"> The benchmarking for the design was done for different 8bit-codes against state-of-the-art FPGA-solutions and showed a gain of up to a factor of six regarding the AT-product, compared to other implementations.

Externe Organisation(en)

Rheinisch-Westfälische Technische Hochschule Aachen (RWTH)

Typ

Artikel

Journal

Advances in Radio Science

Band

3

Seiten

271-276

Anzahl der Seiten

6

ISSN

1684-9965

Publikationsdatum

12.05.2005

Publikationsstatus

Veröffentlicht

Peer-reviewed

Ja

ASJC Scopus Sachgebiete

Elektrotechnik und Elektronik

Elektronische Version(en)

https://doi.org/10.5194/ars-3-271-2005 (Zugang: Offen)