Investigation of stress distribution in via bottom of Cu-via structures with different via form by means of submodeling

verfasst von

Johar Ciptokusumo, Kirsten Weide-Zaage, Oliver Aubel

Abstract

In ULSI multilevel metallizations the via bottom is the main region for the appearance of local stress. This local stress can lead to fractures or porous spots. Out of this concerning the local stress distribution the via bottom region has to be investigated. Due to various technological processes the via shape especially the via bottom geometries are different. In this paper FE-Simulations with respect to the different via bottom geometries and different temperatures of the process steps will be presented. The best via bottom geometry is figured out. The submodeling technique in ANSYS^® is used for these investigations for reduction of simulation time and precise results. The thickness of the barrier has also an influence on the mechanical stress and will be also investigated.

Organisationseinheit(en)

Laboratorium f. Informationstechnologie

Externe Organisation(en)

Global Foundries, Inc.

Typ

Artikel

Journal

Microelectronics reliability

Band

49

Seiten

1090-1095

Anzahl der Seiten

6

ISSN

0026-2714

Publikationsdatum

09.2009

Publikationsstatus

Veröffentlicht

Peer-reviewed

Ja

ASJC Scopus Sachgebiete

Elektronische, optische und magnetische Materialien, Atom- und Molekularphysik sowie Optik, Sicherheit, Risiko, Zuverlässigkeit und Qualität, Physik der kondensierten Materie, Oberflächen, Beschichtungen und Folien, Elektrotechnik und Elektronik

Elektronische Version(en)

https://doi.org/10.1016/j.microrel.2009.07.043 (Zugang: Unbekannt)