Modeling lateral parasitic transistors in smart power ICs

verfasst von

Joerg Oehmen, Markus Olbrich, Lars Hedrich, Erich Barke

Abstract

Negative voltages in power stages of junction-isolated Smart Power ICs turn on parasitic bipolar transistors and inject minority carriers into the substrate, which can affect the functionality of the chip. In order to indicate inadmissible substrate currents and to evaluate protection measures, these parasitic transistors have to be included into a postlayout simulation. A methodology has been developed for automatically generating Verilog-A models for these parasites from layout data. These models account for an inhomogeneous current flow and high electron densities in the substrate. A reasonable tradeoff between convergence behavior and accuracy of the model has been found.

Organisationseinheit(en)

Institut für Mikroelektronische Systeme

Externe Organisation(en)

Goethe-Universität Frankfurt am Main
Institute of Electrical and Electronics Engineers (IEEE)

Typ

Artikel

Journal

IEEE Transactions on Device and Materials Reliability

Band

6

Seiten

408-420

Anzahl der Seiten

13

ISSN

1530-4388

Publikationsdatum

09.2006

Publikationsstatus

Veröffentlicht

Peer-reviewed

Ja

ASJC Scopus Sachgebiete

Elektronische, optische und magnetische Materialien, Sicherheit, Risiko, Zuverlässigkeit und Qualität, Elektrotechnik und Elektronik

Elektronische Version(en)

https://doi.org/10.1109/TDMR.2006.881506 (Zugang: Unbekannt)