Overshoot Prevention in Monolithic GaN by Ultra-Low ESL Gate Loop Design Using Chip-Scale Capacitors and Gate Driver Pull-Up Path Tuning Technique

verfasst von

Niklas Deneke, Bernhard Wicht

Abstract

Despite monolithic integration of GaN gate drivers with the power stage, some parasitic gate loop inductance remains, including connections to off-chip decoupling capacitors. On-chip capacitors, however, complicate the gate loop design by adding another pole to the system. An LC-RC resonant tank replaces the conventional RLC model, which is insufficient. Ultra-low ESL decoupling using chip-scale silicon capacitors bonded directly to the GaN-IC is identified as most effective by measurements for PCB and bonded MLCC and SiCap gate loop decoupling. A voltage-tuning technique-based gate driver, implemented on a GaN-IC, is applied to adapt to the remaining loop inductance and reduce critical overshoot while ensuring fast switching.

Organisationseinheit(en)

Institut für Mikroelektronische Systeme

Typ

Aufsatz in Konferenzband

Seiten

2409-2414

Anzahl der Seiten

6

Publikationsdatum

2024

Publikationsstatus

Veröffentlicht

Peer-reviewed

Ja

ASJC Scopus Sachgebiete

Elektrotechnik und Elektronik

Elektronische Version(en)

https://doi.org/10.1109/APEC48139.2024.10509192 (Zugang: Geschlossen)