FLINT+

A Runtime-Configurable Emulation-Based Stochastic Timing Analysis Framework

verfasst von

Moritz Weißbrich, Guillermo Payá-Vayá, Lukas Gerlach, Holger Blume, A. Najafi, A. García-Ortiz

Abstract

ASICs for Stochastic Computing conditions are designed for higher energy-efficiency or performance by sacrificing computational accuracy due to intentional circuit timing violations. To optimize the stochastic gate-level circuit behavior of a specific design, iterative timing analysis campaigns have to be carried out for a variety of chip temperature- and supply voltage-dependent timing corner cases. However, the application of common event-driven logic simulators usually leads to excessive analysis runtimes, increasing design time for hardware developers. In this paper, a gate-level netlist-oriented FPGA-based timing analysis framework is proposed, offering a runtime-configuration mechanism for emulating different timing corner cases in hardware without requiring multiple FPGA bitstreams. For an exemplary timing analysis campaign of an existing chip design, speed-up factors of up to 267 are achieved while maintaining timing behavior deviations lower than 1.05% to timing simulations.

Organisationseinheit(en)

Institut für Mikroelektronische Systeme

Externe Organisation(en)

Universität Bremen

Typ

Aufsatz in Konferenzband

Seiten

1-8

Anzahl der Seiten

8

Publikationsdatum

09.2017

Publikationsstatus

Veröffentlicht

Peer-reviewed

Ja

ASJC Scopus Sachgebiete

Modellierung und Simulation, Computernetzwerke und -kommunikation, Hardware und Architektur, Energieanlagenbau und Kraftwerkstechnik, Elektrotechnik und Elektronik, Steuerung und Optimierung

Ziele für nachhaltige Entwicklung

SDG 7 – Erschwingliche und saubere Energie

Elektronische Version(en)

https://doi.org/10.1109/PATMOS.2017.8106956 (Zugang: Geschlossen)