HiBRID-SoC

A multi-core SoC architecture for multimedia signal processing

verfasst von

H. J. Stolberg, M. Bereković, L. Friebe, S. Moch, M. B. Kulaczewski, A. Dehnhardt, P. Pirsch

Abstract

The HiBRID-SoC multi-core system-on-chip architecture targets a wide range of multimedia applications with particularly high processing demands, including general signal processing applications, video encoding/decoding, image processing, or a combination of these tasks. For this purpose, the HiBRID-SoC integrates three fully programmable processor cores and various interfaces onto a single chip, all tied to a 64 bit AMBA AHB bus. The processor cores are individually optimized to the particular computational characteristics of different application fields, complementing each other to deliver high performance levels with high flexibility at reduced system cost. The HiBRID-SoC is fabricated in a 0.18 μm 6LM standard-cell technology, occupies about 82 mm/sup 2/, and operates at 145 MHz. An MPEG-4 Advanced Simple Profile decoder in full TV resolution requires about 120 MHz for real-time performance on the HiBRID-SoC, utilizing only two of the three cores.

Organisationseinheit(en)

Institut für Mikroelektronische Systeme

Typ

Aufsatz in Konferenzband

Seiten

189-194

Anzahl der Seiten

6

Publikationsdatum

27.08.2003

Publikationsstatus

Veröffentlicht

Peer-reviewed

Ja

ASJC Scopus Sachgebiete

Elektrotechnik und Elektronik, Signalverarbeitung, Angewandte Mathematik, Hardware und Architektur

Elektronische Version(en)

https://doi.org/10.1109/SIPS.2003.1235667 (Zugang: Geschlossen)