Quantitative analysis of embedded FPGA-architectures for arithmetic

verfasst von

T. Von Sydow, B. Neumann, H. Blume, T. G. Noll

Abstract

Embedding FPGAs (eFPGAs) in modern SoCs provides a high amount of flexibility while high-throughput digital signal processing algorithms can be realised efficiently. An analysis of eFPGA architectures and corresponding structural elements is presented to determine the optimisation potential for eFPGAs tailored to an arithmetic oriented application domain. The applied design flow incorporating an automated layout generation approach and the utilised simulation environment is discussed. An eFPGA macro designed and realised for arithmetic oriented applications is quantitatively compared to an actual commercial FPGA in terms of area, power consumption and delay time. It can be shown that this optimised eFPGA macro outperforms a state of the art commercial device for a couple of arithmetic operators which are commonly applied in arithmetic datapaths.

Externe Organisation(en)

Rheinisch-Westfälische Technische Hochschule Aachen (RWTH)

Typ

Aufsatz in Konferenzband

Seiten

125-131

Anzahl der Seiten

7

Publikationsdatum

04.12.2006

Publikationsstatus

Veröffentlicht

Peer-reviewed

Ja

ASJC Scopus Sachgebiete

Hardware und Architektur, Computernetzwerke und -kommunikation

Elektronische Version(en)

https://doi.org/10.1109/ASAP.2006.56 (Zugang: Geschlossen)