A fair comparison of adders in stochastic regime

verfasst von

Ardalan Najafi, Moritz Weißbrich, Guillermo Payá Vayá, Alberto Garcia-Ortiz

Abstract

The demands of high-speed and power-efficient systems have resulted into the emergence of the approximate computing. Existing approximate circuits as well as stochastic techniques have shown promising advances in improving various figures of merit. However, a through fair comparison of arithmetic units still remains an issue which has not been studied. This paper reviews the prerequisites for a fair comparison of approximate arithmetic units. As one of the key components of arithmetic circuits, adders are the focus of this paper. For the first time in this paper, approximate and exact adders are studied together in the stochastic regime. Simulation results show that both the equal segmentation adder (ESA) and the error tolerant adder type II (ETAII) outperform exact adders working stochastically, if and only if the right configuration and sub-adder architectures are chosen. Otherwise, there is no reason to use the aforementioned architectures. In all, considering the cost-error trade-off, Lower-part OR adder (LOA) has the best behavior in the stochastic regime.

Organisationseinheit(en)

Institut für Mikroelektronische Systeme

Externe Organisation(en)

Universität Bremen

Typ

Aufsatz in Konferenzband

Seiten

1-6

Anzahl der Seiten

6

Publikationsdatum

13.11.2017

Publikationsstatus

Veröffentlicht

Peer-reviewed

Ja

ASJC Scopus Sachgebiete

Modellierung und Simulation, Computernetzwerke und -kommunikation, Hardware und Architektur, Energieanlagenbau und Kraftwerkstechnik, Elektrotechnik und Elektronik, Steuerung und Optimierung

Elektronische Version(en)

https://doi.org/10.1109/patmos.2017.8106990 (Zugang: Geschlossen)