A 50V, 1.45ns, 4.1pJ High-Speed Low-Power Level Shifter for High-Voltage DCDC Converters.

verfasst von

Daniel Lutz, Achim Seidel, Bernhard Wicht

Abstract

The level shifter and the floating gate supply for high-side transistors are a major challenge in high-voltage DCDC converters. This paper presents a high-speed and power-efficient level shifter for voltages of up to 50 V, suitable for both PMOS and NMOS power FETs. A switching node falling edge detection allows both, a sensitive and safe signal detection. This enables a robust operation during steep dv/dt transitions and a power consumption as low as 4.1 pJ per switching cycle, which is a reduction of more than 40 % compared to prior art. An active clamping circuit prevents common mode displacement currents into the high-side supply. The level shifter is implemented in a 180 nm BiCMOS technology. Measurements confirm a 50 V 120 MHz high-speed operation of the level shifter with a rising/falling propagation delay of 1.45 ns/1.3 ns, respectively. The dv/dt robustness has been confirmed by measurements for transitions up to 6 V/ns.

Organisationseinheit(en)

Fachgebiet Mixed-Signal-Schaltungen

Typ

Paper

Seiten

126-129

Anzahl der Seiten

4

Publikationsdatum

2018

Publikationsstatus

Veröffentlicht

Peer-reviewed

Ja

ASJC Scopus Sachgebiete

Elektrotechnik und Elektronik, Instrumentierung

Elektronische Version(en)

https://doi.org/10.1109/esscirc.2018.8494292 (Zugang: Geschlossen)