Contents
The objective of practical course is to design basic image processing algorithms using the hardware description language VHDL. The designed algorithms will be emulated on an FPGA prototyping board. For this purpose, basic knowledge of VHDL is taught and the basic mapping methodology of an algorithm into an FPGA-based hardware prototype is explained as an example. Further contents are the application of a logic analyzer for debugging the designed design as well as the basic internal structure of an FPGA.
The practical course includes four experiments:
1st experiment: Seconds counter with decimal output using a 7-segment display.
2nd experiment: Finite State Machine (FSM) - traffic light circuit and coin changer
3rd experiment: Digital image processing - point operators (inversion, binarization, contrast stretching)
4th experiment: Digital image processing - local image operator (e.g. Gaussian filtering)
SIGNING UP
The registration for the mini-project FPGA prototyping is done by the Institute of Systems Engineering - Department of Real-Time Systems in the context of the hardware internship.
Resources
The practical course documents will be handed out at the introductory event and can be downloaded via Stud.IP (event name: Miniproject FPGA Prototyping).
Introductory Event
The date of the introductory event will be announced during the hardware-lab and is mandatory.
Groups
The project sub-tasks are worked on in a group size of 2 persons at fixed times (4 time hours each).
