Master Theses – Institute of Microelectronic Systems

Design and Evaluation of a High-Current 48V Hybrid DC-DC Converter

Modern compute units in data center applications require 48V-1V DCDC converter with high efficiency and high power density. The thermal design power of these systems keeps increasing, requiring converter implementations with hundreds or even thousands of Ampere of current. The aim of the work is to develop 48V hybrid switched-capacitor DC-DC converter PCBs capable of >100A output current. Multiple high current PCB designs should be designed, populated and measured.

Led by: Joseph Winkler

Team: Rui Li

Year: 2025

Duration: 21.01.2025 - 21.07.2025

Investigation of underdetermined switched-capacitor topologies.

The master's thesis focuses on investigating an underdetermined switched-capacitor topology known as the "Scaled Frequency Doubler." The topology is to be analytically described to identify potential scaling effects in comparison to common topologies. Following the theoretical investigation, practical evaluations will be conducted using an evaluation board. For the evaluation board, a control system based on an FPGA will be developed.

Led by: Tim Kuhlmann

Team: Lukas Böckmann

Year: 2025

Duration: 6.02.2025 - 06.08.2025

Investigation of flying capacitor balancing in multilevel buck converters using current-mode control.

As part of this work, an N-level buck converter model will be developed and analyzed in MATLAB Simulink using current-mode control. A particular focus is on investigating the flying capacitor balancing while considering non-idealities such as finite input impedance, non-ideal current measurement, switching delay, and mismatch. Additionally, a comprehensive literature review of the current state of the art and the latest publications in this area will be conducted.

Led by: Jens Otten

Team: Xiaochen Zhou

Year: 2025

Duration: 24.03.25 - 23.09.25

Entwurf eines hochtemperaturfähigen, energieeffizienten Referenzoszillators

In der Masterarbeit mit dem Titel "Design and Evaluation of an Integrated Low-Power, High-Temperature-Capable, Multi-Megahertz Reference Clock Generator" wird ein integrierter Taktgenerator für einen Temperaturbereich von -40°C bis 175°C entwickelt. Angestrebt wird ein Temperaturkoeffizient von unter 20 ppm/°C sowie eine Leistungsaufnahme von etwa 1 µW/MHz. Diese Werte entsprechen dem aktuellen Stand der Technik, jedoch bei einem deutlich erweiterten Temperaturbereich. Ein temperaturstabiler und energieeffizienter Taktgenerator ist ein zentrales Element für rauscheffiziente Switched-Capacitor-Filter in analogen Sensor-Frontends.

Led by: Hendrik Siemßen

Team: Zeen Wang

Year: 2025

Duration: 06.11.2024-06.05.2025

Investigation and evaluation of the implementation variants of a massively parallel vector processor for the Intel Arria 10 FPGA architecture

The task in this thesis is to port the VPRO vector processor developed at the institute and optimized for Xilinx FPGAs to the Intel Arria 10 FPGA architecture. To achieve the highest possible computing power, the computing cores of the vector processor should be optimized for the FPGA architecture.

Team: -

Implementation of an Automatic Tool for Efficiently Mapping Convolutional Neural Networks to a Vector Processor Architecture

The task of this work is to implement a CNN mapping tool, which uses a common CNN description (e.g. for tensorflow) as input and generates the according plain C code for the VPRO processor.

Team: Xingrui Li