A gate sizing method for glitch power reduction.

authored by

Lei Wang, Markus Olbrich, Erich Barke, Thomas Büchner, Markus Bühler, Philipp V. Panitz

Organisation(s)

Mixed-Signal Circuits Section

Type

Paper

Pages

24-29

Publication date

2011

Publication status

Published

Peer reviewed

Yes

Electronic version(s)

https://doi.org/10.1109/SOCC.2011.6085070 (Access: Unknown)