Hierarchical Verification of AMS Systems With Affine Arithmetic Decision Diagrams

authored by

Carna Zivkovic, Christoph Grimm, Markus Olbrich, Oliver Scharf, Erich Barke

Abstract

Formal methods are a promising alternative to simulation-based verification of mixed-signal systems. However, in practice, such methods fail to scale with heterogeneity and complexity of today's analog/mixed-signal systems. Furthermore, it is unclear how they can be integrated into existing verification flows. This paper shows a path to overcome these obstacles. The idea is to use a hierarchical verification flow, in which components can be verified by formal methods or by multirun simulation. To transport verification results across hierarchies, we represent parameters and properties by affine arithmetic decision diagrams. We study to which extent this approach fulfills the needs of practical application by the verification of a phase-locked loop of an IEEE 802.15.4 transceiver system.

Organisation(s)

Mixed-Signal Circuits Section

External Organisation(s)

University of Kaiserslautern

Type

Article

Journal

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volume

38

Pages

1785-1798

No. of pages

14

Publication date

10.2019

Publication status

Published

Peer reviewed

Yes

ASJC Scopus subject areas

Software, Computer Graphics and Computer-Aided Design, Electrical and Electronic Engineering

Electronic version(s)

https://doi.org/10.1109/tcad.2018.2864238 (Access: Closed)