Prof. Dr.-Ing. Holger Blume

Phone

+49 511 762 19640

Fax

+49 511 762 19601

holger.blumeims.uni-hannover.de

Address

Appelstr. 4
30167 Hannover

Phone

+49 511 762 19640

Fax

+49 511 762 19601

holger.blumeims.uni-hannover.de

Address

Appelstr. 4
30167 Hannover

Career

Holger Blume, born in 1967, studied electrical engineering at the University of Dortmund from 1987 to 1992. During his studies he was a scholarship holder of the German National Academic Foundation. From 1993 to 1996 he was a research assistant in the Circuits for Information Processing group at the University of Dortmund (Prof. Dr. H. Schröder). From 1996-1998 he was employed as a research associate at the Informatik Centrum Dortmund (ICD). In 1997, he received his PhD with honors from the University of Dortmund on the topic of "Nonlinear Fault-Tolerant Interpolation of Intermediate Images".

From 1998 to 2008, he worked first as a senior engineer and later as an academic senior councillor at the Department of General Electrical Engineering and Data Processing Systems at RWTH Aachen University (Prof. Dr. T. G. Noll). In February 2008 he habilitated there with a thesis on "Exploration of the Design Space for Heterogeneous Architectures for Digital Video Signal Processing".

In July 2008, he followed a call to Leibniz Universität Hannover where he has been working since then as professor for "Architectures and Systems" and as managing director of the Institute for Microelectronic Systems (IMS).

Publications

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Showing results 1 - 20 out of 366

An Intelligent and Efficient Workflow for Path-Oriented 3D Bioprinting of Tubular Scaffolds. / Baroth, Timo; Loewner, Sebastian; Heymann, Henrik et al.
In: 3D Printing and Additive Manufacturing, Vol. 11, No. 1, 15.02.2024, p. 323-332.
Research output: Contribution to journal › Article › Research › peer review
More...

Enhancing RISC-V Processor Performance in Harsh Environments through Data Cache Optimization. / Frühauf, Jan-Luca; Hawich, Malte; Blume, Holger Christoph.
2024 Panhellenic Conference on Electronics & Telecommunications (PACET). IEEE, 2024. p. 1-4 (Panhellenic Conference on Electronics & Telecommunications (PACET)).
Research output: Chapter in book/report/conference proceeding › Conference contribution › Research › peer review
More...

High Temperature In-Order RISC-V Processor with Heterogeneous Pipeline and Out-of-Order Write-Back Mechanism. / Hawich, Malte; Blume, Holger Christoph; Szücs, Jan.
2024 Kleinheubach Conference. 2024. p. 1-4.
Research output: Chapter in book/report/conference proceeding › Conference contribution › Research › peer review
More...

Improving Clock Frequencies in ASIC Designs through Semi-Automatic Register Placement and Advanced Retiming. / Hawich, Malte; Klein, Simon Christian; Stuckenberg, Tobias et al.
2024 Panhellenic Conference on Electronics & Telecommunications (PACET). 2024. p. 1-6 (Panhellenic Conference on Electronics & Telecommunications (PACET)).
Research output: Chapter in book/report/conference proceeding › Conference contribution › Research › peer review
More...

Single Snapshot Array Interpolation for Angular Estimation in Automotive Radar Applications. / Jauch, Alisa; Meinl, Frank; Blume, Holger.
2024 15th German Microwave Conference, GeMiC 2024. Institute of Electrical and Electronics Engineers Inc., 2024. p. 257-260.
Research output: Chapter in book/report/conference proceeding › Conference contribution › Research › peer review
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Enhancing a Hearing Aid Processor with ISA Extensions Supporting Flexible Fixed-Point Formats. / Karrenbauer, Jens; Schönewald, Sven; Klein, Simon et al.
Proceedings - 2024 IEEE 35th International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2024. 2024. p. 176-183 (EEE International Conference on Application-Specific Systems, Architectures, and Processors).
Research output: Chapter in book/report/conference proceeding › Conference contribution › Research › peer review
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SmartHeaP- A High-level Programmable and Customized Hearing Aid System on Chip Integrated in a Research Hearing Aid Prototype. / Karrenbauer, Jens; Schonewald, Sven; Klein, Simon et al.
In: IEEE Transactions on Biomedical Circuits and Systems, 2024.
Research output: Contribution to journal › Article › Research › peer review
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Multi-Level Prototyping of a Vertical Vector AI Processing System. / Kautz, Frederik; Gesper, Sven; Thieu, Gia Bao et al.
Proceedings - 2024 IEEE 35th International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2024. Institute of Electrical and Electronics Engineers Inc., 2024. p. 1-2 (Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors).
Research output: Chapter in book/report/conference proceeding › Conference contribution › Research › peer review
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Ethernet-based lighting-architecture: Image stabilization for high-resolution light functions. / Pfleiderer, Richard; Schleusner, Jens Karsten; Blume, Holger Christoph et al.
2024. 1-29 Automotive Ethernet Congress, München, Bavaria, Germany.
Research output: Contribution to conference › Slides to presentation › Research › peer review
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Non-linear Filtering Techniques for Improving Accurate Vehicle Angle Determination. / Pfleiderer, Richard; Ramsdorf, Jannes; Boländer, Yannis et al.
2024 Kleinheubach Conference. 2024.
Research output: Chapter in book/report/conference proceeding › Conference contribution › Research › peer review
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Design Space Exploration of Semantic Segmentation CNN SalsaNext for Constrained Architectures. / Renke, Oliver; Riggers, Christoph; Karrenbauer, Jens et al.
Proceedings - 2024 IEEE 35th International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2024. 2024. p. 28-29 (IEEE International Conference on Application-Specific Systems, Architectures, and Processors).
Research output: Chapter in book/report/conference proceeding › Conference contribution › Research › peer review
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Moderne Automobilelektronik : KI-Hardware für die Sensorsignalverarbeitung. / Riggers, Christoph; Lüders, Matthias; Weddige, Sousa et al.
In: Uni-Magazin, Hannover, Vol. 2024, No. 01|02, 2024.
Research output: Contribution to journal › Article › Transfer
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PTP-Synchronized Tri-Level Sync Generation for Networked Multi-Sensor Systems. / Riggers, Christoph; Schleusner, Jens; Renke, Oliver et al.
2024 IEEE 30th International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA). 2024. p. 91-96.
Research output: Chapter in book/report/conference proceeding › Conference contribution › Research › peer review
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An Optimized FPGA Implementation of SAR Backprojection Autofocus. / Rother, Niklas; Fahnemann, Christian; Blume, Holger.
EUSAR 2024 - 15th European Conference on Synthetic Aperture Radar. Institute of Electrical and Electronics Engineers Inc., 2024. p. 44-49 (Proceedings of the European Conference on Synthetic Aperture Radar, EUSAR).
Research output: Chapter in book/report/conference proceeding › Conference contribution › Research › peer review
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Learning of Multimodal Point Descriptors in Radar and LIDAR Point Clouds. / Rotter, Jan M.; Cohrs, Simon; Blume, Holger et al.
2024 IEEE International Conference on Multisensor Fusion and Integration for Intelligent Systems (MFI). 2024. (IEEE International Conference on Multisensor Fusion and Integration for Intelligent Systems).
Research output: Chapter in book/report/conference proceeding › Conference contribution › Research › peer review
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Sub-Microsecond Time Synchronization for Network-Connected Microcontrollers. / Schleusner, Jens; Fahnemann, Christian; Pfleiderer, Richard et al.
2024 IEEE International Conference on Consumer Electronics (ICCE). 2024. (Digest of Technical Papers - IEEE International Conference on Consumer Electronics).
Research output: Chapter in book/report/conference proceeding › Conference contribution › Research › peer review
More...

Optimizing RISC-V Processor Performance with Adaptive Execution Unit Lengths in Harsh Environment Conditio. / Szücs, Jan; Hawich, Malte; Blume, Holger Christoph.
2024 Panhellenic Conference on Electronics & Telecommunications (PACET). 2024. p. 1-5.
Research output: Chapter in book/report/conference proceeding › Conference contribution › Research › peer review
More...

An Affordable Autonomous 2U-Greenhouse for Plant Research in low-gravity Environments. / Woiwode, Dominik; Marten, Jakob Frederik; Behrens, Dörthe et al.
2024. Poster session presented at 28th ELGRA Biennial Symposium & General Assembly, Liverpool, United Kingdom (UK).
Research output: Contribution to conference › Poster › Research › peer review
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Exploiting Subword Permutations to Maximize CNN Compute Performance and Efficiency. / Beyer, Michael; Gesper, Sven; Guntoro, Andre et al.
Proceedings - 2023 IEEE 34th International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2023. Institute of Electrical and Electronics Engineers Inc., 2023. p. 61-68 (Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors; Vol. 2023-July).
Research output: Chapter in book/report/conference proceeding › Conference contribution › Research › peer review
More...

Online Quantization Adaptation for Fault-Tolerant Neural Network Inference. / Beyer, Michael; Borrmann, Jan Micha; Guntoro, Andre et al.
Computer Safety, Reliability, and Security: 42nd International Conference, SAFECOMP 2023, Toulouse, France, September 20–22, 2023, Proceedings. ed. / Jérémie Guiochet; Stefano Tonetta; Friedemann Bitsch. Springer International Publishing AG, 2023. p. 243–256 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 14181 LNCS).
Research output: Chapter in book/report/conference proceeding › Contribution to book/anthology › Research › peer review
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Research Projects
Processor Architectures

High Temperature Measurement While Drilling

The goal of the research is an MWD processor system for drilling tools used for geothermal drilling in ambient temperatures up to 300 °C. The processing of the project includes research aspects in the fields of hardware design, fault tolerance of digital systems and ASIC design.

Led by: Prof. Dr.-Ing. H. Blume

Team: Dipl.-Ing. Rochus Nowosielski

Year: 2014

Duration: 2012-2014

GEBO - High Temperature Electronic

In this project, the design of mixed-signal circuits for signal processing is studied under high temperature conditions. For this, research on analog circuits and digital signal processing architectures will be conducted in order to adapt common design approaches to the requirements of high temperature technology.

Led by: Prof. Dr.-Ing. H. Blume

Team: Dipl.-Ing. Rochus Nowosielski

Year: 2014

Duration: 2009-20111

OPARO

In the development of integrated, programmable circuits, the optimization of power dissipation and temperature distribution is becoming increasingly important. So far, however, these can only be determined by very time-consuming simulations. Therefore, precise models for the determination of power dissipation shall be developed and mapped together with the functional emulation on FPGAs. By accelerating the determination of power dissipation and temperature distribution, specific optimizations of the architecture and the application code can then be made taking real input data into account.

Led by: Prof. Dr.-Ing. H. Blume

Team: Dipl.-Wirtsch.-Ing. Sebastian Hesselbarth

Year: 2014

Hearing4All

The joint venture "Hearing4all" that the IMS-AS participates in with multiple sub-projects, has been chosen as one of the federal cluster of excellence projects Friday June 15th 2012. In the scope of this project the IMS-AS aims to develop high-performance and low-power processor architectures for digital hearing systems, such as cochlear implants or hearing aids.

Led by: Prof. Dr.-Ing. H. Blume, Jun.-Prof. Dr.-Ing. G. Payá-Vayá

Team: M.Sc. C. Seifert, Dipl.-Ing. L. Gerlach

Year: 2015

Duration: November 2012 - December 2018

Stochastic Processor

Stochastic computing has recently emerged as a promising approach for designing energy-efficient embedded hardware systems, taking into account the ability of many applications (e.g., computer vision) to tolerate the loss of precision in the computed results. Rather than designing the hardware for worst case scenarios featuring expensive guard-bands, designers can relax the implementation constraints and deliberately expose hardware variability, obtaining significant processing performance improvements and energy benefits.

Led by: Jun.-Prof. Dr.-Ing. G. Payá-Vayá, Prof. Dr.-Ing. Holger Blume

Team: M.Sc. Moritz Weißbrich

Year: 2015

Funding: Deutsche Forschungsgemeinschaft (DFG)

Duration: February 2016 - January 2019

TETRACOM

Nowadays, continuous development of digital signal processing applications, e.g., video-based advanced driver assistance systems, are pushing the limits of existing embedded systems and are forcing system developers to spend more time on code optimization. These applications often involve complex mathematical functions like trigonometric, logarithmic, exponential, or square root operations. In particular, these functions can only efficiently be computed on standard general purpose embedded processors, using highly optimized, processor specific arithmetic evaluation software libraries. Another alternative is to extend the embedded processor architectures with a specific hardware accelerator.

Led by: Jun.-Prof. Dr.-Ing. G. Payá-Vayá

Team: Dipl.-Ing. S. Nolting, Dipl.-Ing. L. Gerlach

Year: 2016

Duration: January 2016 - July 2016

Multi-Energy Harvesting (MEH) - A Flexible Platform for Energy Harvesting in Home Automation

In this project, a platform concept for intelligent home automation components is developed, which can serve as a basis for next-generation sensors and actors. The main characteristic of this platform concept is ultra-low power consumption and ultra-low voltage operation. In combination with harvested energy from multiple sources (multi-energy harvesting), an extended lifetime and reduced battery cell requirements become possible compared to current systems.

Led by: Prof. Dr.-Ing. H. Blume, Prof. Dr.-Ing. B. Wicht, apl. Prof. Dr.-Ing. G. Payá Vayá

Team: M.Sc. Moritz Weißbrich, M.Sc. Lars-Christian Kähler

Year: 2019

Funding: BMBF

Duration: October 2018 - March 2021

EcoMobility

During the European project "EcoMobility", the IMS will improve autonomous electric vehicles in regards to sustainability, connectivity and safety together with 46 partners from all over Europe. The IMS will especially focus on intelligent scheduling of tasks on heterogeneous processor systems.

Led by: Prof. Dr.-Ing. Holger Blume, M.Sc. Matthias Lüders

Team: M.Sc. Jonas Hollmann

Year: 2023

Funding: KDT JU

Duration: 2023-2025

Analog/Mixed-Signal-Design

GEBO - High Temperature Electronic

In this project, the design of mixed-signal circuits for signal processing is studied under high temperature conditions. For this, research on analog circuits and digital signal processing architectures will be conducted in order to adapt common design approaches to the requirements of high temperature technology.

Led by: Prof. Dr.-Ing. H. Blume

Team: Dipl.-Ing. Rochus Nowosielski

Year: 2014

Duration: 2009-20111

Multi-Energy Harvesting (MEH) - A Flexible Platform for Energy Harvesting in Home Automation

In this project, a platform concept for intelligent home automation components is developed, which can serve as a basis for next-generation sensors and actors. The main characteristic of this platform concept is ultra-low power consumption and ultra-low voltage operation. In combination with harvested energy from multiple sources (multi-energy harvesting), an extended lifetime and reduced battery cell requirements become possible compared to current systems.

Led by: Prof. Dr.-Ing. H. Blume, Prof. Dr.-Ing. B. Wicht, apl. Prof. Dr.-Ing. G. Payá Vayá

Team: M.Sc. Moritz Weißbrich, M.Sc. Lars-Christian Kähler

Year: 2019

Funding: BMBF

Duration: October 2018 - March 2021

Design Space Exploration

EFdiS – Use of airborne SAR with digital interface

The goal of this research project is the processing of FMCW sensor signals. The first step is intended to digitize the analog data on board through a suitable expansion card. In the second step, the digitized data is to be processed on board, and thus converted to an aerial image.

Led by: Prof. Dr.-Ing. H. Blume

Team: Dipl.-Ing. M. Wielage

Year: 2014

Duration: October 2012 - December 2014

OPARO

In the development of integrated, programmable circuits, the optimization of power dissipation and temperature distribution is becoming increasingly important. So far, however, these can only be determined by very time-consuming simulations. Therefore, precise models for the determination of power dissipation shall be developed and mapped together with the functional emulation on FPGAs. By accelerating the determination of power dissipation and temperature distribution, specific optimizations of the architecture and the application code can then be made taking real input data into account.

Led by: Prof. Dr.-Ing. H. Blume

Team: Dipl.-Wirtsch.-Ing. Sebastian Hesselbarth

Year: 2014

Digital Video-processing for automation in agriculture

Within this project, algorithms are developed, architectures explored and a final hardware-platform designed and evaluated. The overall system will be tested in a field test.

Led by: Prof. Dr.-Ing. H. Blume

Team: J. Hartig, S. Gesper

Year: 2019

Duration: a 2017-2019

Compact Realtime SAR-Image processor

The goals of this project are the generation and compression of high resolution Synthetic Aperture Radar (SAR) images under real time conditions. Compared to camera based electro-optical sensors, a SAR system operates almost independent from daylight and weather conditions. State-of-the-art SAR sensor systems achieve spatial resolutions up to 10 cm at 10 km altitude. By using FPGAs for high performance digital signal processing tasks, aerial images can be generated in real time even in case of very large image dimensions.

Led by: Prof. Dr.-Ing. H. Blume

Team: F. Cholewa, C. Fahnemann, N. Rother

Year: 2020

Duration: 2008-2020

Driver Assistance Systems

OpenFAS

In the scope of this project, a library of modules for driver assistence systems, based on a multicore processor architecture will be created. The project is in collaboration with the videantis corporation.

Led by: Prof. Dr.-Ing. Holger Blume

Team: Dipl.-Ing. Christopher Bartels

Year: 2012

Funding: "Zentrales Innovationsprogramm Mittelstand" des Bundesministeriums für Wirtschaft und Technologie (BMWi)

Duration: Juni 2012 - Oktober 2013

DESERVE - Development Platform for Safe and Efficient Drive

DESERVE is a project funded by the European Union. The aim of the project is the promotion and evolution of advanced driver assistance systems (ADAS). These systems are devoted to support the driver in the safe control of the vehicle. For this purpose, the DESERVE platform is planned to be developed. This platform will be the base for future development of advanced driver assistance systems in Europe.

Led by: Prof. Dr.-Ing. H. Blume, apl. Prof. Dr.-Ing. G. Payá Vayá

Team: Florian Giesemann, Frank Meinl, Nico Mentzer

Year: 2013

Funding: Europäische Union, Bundesministerium für Bildung und Forschung

Duration: September 2012 - August 2015

ASEV

The goal of this sub-project of the BMBF project "Automatic Situation Interpretation for Event Triggered Video Surveillance" is to elaborate a concept for a hardware architecture that enables a SIFT (Scale Invariant Feature Transform) feature extraction under application-specific processing conditions as performance and power consumption. SIFT features offer a good basis for robust object identification and tracking for event triggered video surveillance. The field of application is thereby the airport apron, which is highly relevant to security. The concept was implemented on a FPGA-based hardware platform to build a demonstrator which was tested at the end of the project at the airport of Braunschweig.

Led by: Prof. Dr.-Ing. H. Blume, Jun.-Prof. Dr.-Ing. G. Payá-Vayá

Team: Dipl.-Ing. Nico Mentzer

Year: 2014

Funding: Bundesministerium für Bildung und Forschung (BMBF)

Duration: Mai 2010 - April 2013

Efficient Hardware Architectures for Fast Image Sequence Analysis

In practice, general reliability of modern driver assistance systems under arbitrary traffic, weather and illumination conditions often is a problem. Because more robust algorithms are computationally very intensive, this project deals with the examination of heterogenous hardware architectures and the evaluation of new mechanisms for complex applications in the field of camera-based driver assistance.

Led by: Prof. Dr.-Ing. H. Blume

Team: Julian Hartig

Year: 2014

Funding: Hans L. Merkle Stiftung

Duration: February 2014 - February 2017

mDAS - Implementation of a real-time demonstrator for multicore-based driver assistance systems

The goal of this Project is the conceptual design of a real-time mutlicore-based demonstrator for video-based driver assistance algorithms. Therefore, different performance metrics will be displayed in order to compare platform-specific performance characteristics.

Led by: Prof. Dr.-Ing. Holger Blume

Team: Dipl.-Ing. Jakob Arndt

Year: 2014

Funding: Siemens AG

Duration: February 2014 - August 2014

ZIM Dream Chip Technologies GmbH

In cooperation with Dream Chip Technologies GmbH, Garben, Germany, the Institute of Microelectronic Systems develops with funding from the Federal Ministry of Economic Affairs and Energy a camera system with integrated algorithms for high quality real time motion estimation in the area of driver assistance systems.

Led by: Prof. Dr.-Ing. H. Blume

Team: Gregor Schewior, Nicolai Behmann

Year: 2015

Funding: Bundesministerium für Wirtschaft und Energie

Duration: September 2015 - December 2016

THINGS2DO - THIN but Great Silicon 2 Design Objects

THINGS2DO is an ENIAC project, funded by the European Union and the Federal Ministry of Education and Research. The project aims to develop the new Fully Depleted Silicon On Insulator (FD-SOI) technology and the corresponding tool environment for high efficient and highly integrated circuits. The capabilities of the technology are further demonstrated through a demonstrator in the area of Advanced Driver Assistance Systems (ADAS).

Led by: Prof. Dr.-Ing. H. Blume

Team: Gregor Schewior, Nicolai Behmann

Year: 2016

Funding: Europäische Union, Bundesministerium für Bildung und Forschung

Duration: February 2016 - March 2018

GreenML

The project "GreenML" aims to exemplify a holistic AI design process by the highly efficient and resource-optimized implementation of essential FAS functions like object detection, object classification, and scene contextualization on particular hardware. Deep Learning (DL) has become a central approach for modern AI applications. Even though energy-efficient DL has become a target in research, currently isolated solutions are often created that do not unleash the full potential for resource-efficient AI. In this project, we will focus on a holistic approach: from hardware to efficient coding and transfer of data and models to dynamic and resource-adaptive software to enable multi-criteria optimization of all facets of an AI-enabled system. As an example, we demonstrate the potential of this approach using the scenario of a modern driver assistance system (FAS). With about 67 million registered vehicles and increased e-mobility, saving required energy by combining efficient algorithms, communication, and hardware is urgently needed. Our "Green Assisted Driving" project addresses different energy consumption, safety, and flexibility metrics. The consortium combines low-power hardware, learning of efficient representations from large data sets, hyperparameter optimization, and network design using AutoML, as well as methods of transfer learning, semi-supervised learning, and network pruning to prototype highly efficient and dynamically controllable models on a FAS. and demonstrate the savings potential of a holistic approach.

Led by: Prof. Dr.-Ing. habil H. Blume

Team: Matthias Lüders

Year: 2023

Duration: 2023-2026

EcoMobility

During the European project "EcoMobility", the IMS will improve autonomous electric vehicles in regards to sustainability, connectivity and safety together with 46 partners from all over Europe. The IMS will especially focus on intelligent scheduling of tasks on heterogeneous processor systems.

Led by: Prof. Dr.-Ing. Holger Blume, M.Sc. Matthias Lüders

Team: M.Sc. Jonas Hollmann

Year: 2023

Funding: KDT JU

Duration: 2023-2025

Biomedical Engineering

Real-time, low-latency sonification of complex movements

The goal of this research project in the field of biomedical engineering is to generate an auditory feedback (sonification) of human movements. The IMS focuses on examing the performance of different hardware platforms for this application. Relevant performance parameters are the platforms power dissipation and the overall latency. Finally, the project goal is to enhance stroke rehabilitation by additionally providing auditory arm movement feedback. This could lead to shortened rehabilitation periods. Furthermore, the mobile hardware platform developed at the IMS allows home based rehabilitation.

Led by: Prof. Dr.-Ing. Blume

Team: Dipl.-Ing. (FH) H.-P. Brückner

Year: 2013

Funding: Europäischer Fonds für regionale Entwicklung (EFRE)

Duration: February 2011 - June 2013

BIOFABRICATION for NIFE

BIOFABRICATION for NIFE ist ein interdisciplinary research network between the Hanover Medical School, the Leibniz University of Hanover and the Hanover University of Music, Drama and Media. The goal of this research network is to achieve methods for growing biocompatible organic implants with heavily reduced rejection reactions.

Led by: Prof. Dr.-Ing. Blume

Team: Dipl.-Ing. Christian Leibold

Year: 2014

Funding: VolkswagenStiftung and County Lower Saxony

Duration: May 2013 - June 2018

Hearing4All

The joint venture "Hearing4all" that the IMS-AS participates in with multiple sub-projects, has been chosen as one of the federal cluster of excellence projects Friday June 15th 2012. In the scope of this project the IMS-AS aims to develop high-performance and low-power processor architectures for digital hearing systems, such as cochlear implants or hearing aids.

Led by: Prof. Dr.-Ing. H. Blume, Jun.-Prof. Dr.-Ing. G. Payá-Vayá

Team: M.Sc. C. Seifert, Dipl.-Ing. L. Gerlach

Year: 2015

Duration: November 2012 - December 2018

Optogenetic

Within this cooperation with the Institute of Technical Chemistry and the Institute of Quantum Optics of the Leibniz Universität Hannover, methods are being studied to control the behavior of intracellular processes from the outside with light. Optogenetics can be used to specifically modify light-insensitive cells in order to respond to the influence of light. Due to the common previous experience between the project partners, especially optogenetic questions in the context of tissue engineering are focussed.

Led by: Prof. Dr.-Ing. Holger Blume

Team: Marc-Nils Wahalla, Dipl.-Ing.

Year: 2016

Efficient Real-time Processing of EEG-Signals

A brain-computer interface (BCI) is a system that generates signals to control an artificial system based on measurements of the activity of the central nervous system, for example, to replace, enhance or supplement certain tasks of human action. Modern BCIs are often based on the decoding or interpretation of EEG signals, as such systems are both non-invasive and cost-effectively available. These sensors detect a variety of independent, superimposed signals that make their immediate use for controlling a digital system difficult. Therefore, each application and corresponding application environment requires specifically designed and customized algorithms. This project therefore investigates methods for the efficient real-time processing of EEG signals. For this purpose, the Institute of Microelectronic Systems is developing a complete system of dedicated, configurable hardware in combination with a signal-processing framework specially adapted for the processing of EEG signals.

Led by: Prof. Dr.-Ing. Holger Blume, Jun.-Prof. Dr.-Ing. G. Payá-Vayá

Team: Marc-Nils Wahalla, Dipl.-Ing.

Year: 2017

ZIM D-Sense - Development of a Testing System for the Diagnosis of Sensorimotor Regulation Abilities in Athletes

The aim of the project is to develop a mobile diagnostics system which can be used to to assess the sensorimotor regulation abilities in athletes. The system should consist of multiple sensor units and allow the athlete or coach to quickly and precisely perform different functional sensorimotor tests. The sensor units can be placed at different points on or next to the subject's body, depending on the concrete test being performed. Also depending on the test, different algorithms are to be used for classifying and evaluating the measurements from the sensor units. A database helps the user to interpret the test results and provides reference values for risk assessments regarding injuries.

Led by: Prof. Dr.-Ing. H. Blume

Team: M.Sc. Fritz Webering

Year: 2017

Funding: „Zentrales Innovationsprogramm Mittelstand“ of the BMWi - Federal Ministry for Economic Affairs and Energy

Duration: 2017-2019

System Design

GEBO - High Temperature Electronic

In this project, the design of mixed-signal circuits for signal processing is studied under high temperature conditions. For this, research on analog circuits and digital signal processing architectures will be conducted in order to adapt common design approaches to the requirements of high temperature technology.

Led by: Prof. Dr.-Ing. H. Blume

Team: Dipl.-Ing. Rochus Nowosielski

Year: 2014

Duration: 2009-20111

Efficient Real-time Processing of EEG-Signals

A brain-computer interface (BCI) is a system that generates signals to control an artificial system based on measurements of the activity of the central nervous system, for example, to replace, enhance or supplement certain tasks of human action. Modern BCIs are often based on the decoding or interpretation of EEG signals, as such systems are both non-invasive and cost-effectively available. These sensors detect a variety of independent, superimposed signals that make their immediate use for controlling a digital system difficult. Therefore, each application and corresponding application environment requires specifically designed and customized algorithms. This project therefore investigates methods for the efficient real-time processing of EEG signals. For this purpose, the Institute of Microelectronic Systems is developing a complete system of dedicated, configurable hardware in combination with a signal-processing framework specially adapted for the processing of EEG signals.

Led by: Prof. Dr.-Ing. Holger Blume, Jun.-Prof. Dr.-Ing. G. Payá-Vayá

Team: Marc-Nils Wahalla, Dipl.-Ing.

Year: 2017

ZIM D-Sense - Development of a Testing System for the Diagnosis of Sensorimotor Regulation Abilities in Athletes

The aim of the project is to develop a mobile diagnostics system which can be used to to assess the sensorimotor regulation abilities in athletes. The system should consist of multiple sensor units and allow the athlete or coach to quickly and precisely perform different functional sensorimotor tests. The sensor units can be placed at different points on or next to the subject's body, depending on the concrete test being performed. Also depending on the test, different algorithms are to be used for classifying and evaluating the measurements from the sensor units. A database helps the user to interpret the test results and provides reference values for risk assessments regarding injuries.

Led by: Prof. Dr.-Ing. H. Blume

Team: M.Sc. Fritz Webering

Year: 2017

Funding: „Zentrales Innovationsprogramm Mittelstand“ of the BMWi - Federal Ministry for Economic Affairs and Energy

Duration: 2017-2019

Reconfigurable Architectures

Circuit Design and Physical Design for a Novel FPGA Architecture

Evaluation and analysis of the implemtability and performance of a new type of field programmable gate array (FPGA).

Led by: Prof. Dr.-Ing. H. Blume, apl. Prof. Dr.-Ing. G. Payá Vayá

Team: B. Bredthauer, C. Spindeldreier

Year: 2013

Funding: Federal Ministry of Education and Reserach

Duration: May 2013 - June 2014

TUKUTURI

In the TUKUTURI-project, a for ASIC-synthesis optimized VHDL-description of a soft core processor architecture will be optimized for FPGA synthesis. The suitability of special functional units for specific applications with regard to performance and area consumption will be analyzed.

Led by: Jun.-Prof. Dr.-Ing. G. Payá-Vayá

Team: M. Sc. Florian Giesemann

Year: 2014

Funding: Wege in die Forschung II

Prof. Dr.-Ing. Holger Blume

Career

Processor Architectures

Analog/Mixed-Signal-Design

Design Space Exploration

Driver Assistance Systems

Biomedical Engineering

System Design

Reconfigurable Architectures