Investigation of stress distribution in via bottom of Cu-via structures with different via form by means of submodeling

authored by

Johar Ciptokusumo, Kirsten Weide-Zaage, Oliver Aubel

Abstract

In ULSI multilevel metallizations the via bottom is the main region for the appearance of local stress. This local stress can lead to fractures or porous spots. Out of this concerning the local stress distribution the via bottom region has to be investigated. Due to various technological processes the via shape especially the via bottom geometries are different. In this paper FE-Simulations with respect to the different via bottom geometries and different temperatures of the process steps will be presented. The best via bottom geometry is figured out. The submodeling technique in ANSYS^® is used for these investigations for reduction of simulation time and precise results. The thickness of the barrier has also an influence on the mechanical stress and will be also investigated.

Organisation(s)

Laboratorium f. Informationstechnologie

External Organisation(s)

Global Foundries, Inc.

Type

Article

Journal

Microelectronics reliability

Volume

49

Pages

1090-1095

No. of pages

6

ISSN

0026-2714

Publication date

09.2009

Publication status

Published

Peer reviewed

Yes

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials, Atomic and Molecular Physics, and Optics, Safety, Risk, Reliability and Quality, Condensed Matter Physics, Surfaces, Coatings and Films, Electrical and Electronic Engineering

Electronic version(s)

https://doi.org/10.1016/j.microrel.2009.07.043 (Access: Unknown)