Modeling lateral parasitic transistors in smart power ICs

authored by

Joerg Oehmen, Markus Olbrich, Lars Hedrich, Erich Barke

Abstract

Negative voltages in power stages of junction-isolated Smart Power ICs turn on parasitic bipolar transistors and inject minority carriers into the substrate, which can affect the functionality of the chip. In order to indicate inadmissible substrate currents and to evaluate protection measures, these parasitic transistors have to be included into a postlayout simulation. A methodology has been developed for automatically generating Verilog-A models for these parasites from layout data. These models account for an inhomogeneous current flow and high electron densities in the substrate. A reasonable tradeoff between convergence behavior and accuracy of the model has been found.

Organisation(s)

Institute of Microelectronic Systems

External Organisation(s)

Goethe University Frankfurt
Institute of Electrical and Electronics Engineers (IEEE)

Type

Article

Journal

IEEE Transactions on Device and Materials Reliability

Volume

6

Pages

408-420

No. of pages

13

ISSN

1530-4388

Publication date

09.2006

Publication status

Published

Peer reviewed

Yes

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials, Safety, Risk, Reliability and Quality, Electrical and Electronic Engineering

Electronic version(s)

https://doi.org/10.1109/TDMR.2006.881506 (Access: Unknown)