VLSI architectures for hierarchical block matching algorithms

authored by

T. Komarek, P. Pirsch

Abstract

An application-specific multiprocessor system is investigated for real-time implementation of the hierarchical block matching algorithm. The proposed architecture is based on parallel processing units and local memories which are globally preloaded via a common bus. The performance is estimated for the data transfer and the parallel computation time schedule.

Organisation(s)

Architectures and Systems Section

Type

Conference article

Journal

Proceedings - IEEE International Symposium on Circuits and Systems

Volume

1

Pages

45-48

No. of pages

4

ISSN

0271-4310

Publication date

1990

Publication status

Published

Peer reviewed

Yes

ASJC Scopus subject areas

Electrical and Electronic Engineering