HiBRID-SoC
A multi-core SoC architecture for multimedia signal processing
- authored by
- Hans Joachim Stolberg, Mladen Bereković, Sören Moch, Lars Friebe, Mark B. Kulaczewski, Sebastian Flügel, Heiko Klußmann, Andreas Dehnhardt, Peter Pirsch
- Abstract
The HiBRID-SoC multi-core system-on-chip architecture targets a wide range of multimedia applications with particularly high processing demands, including general signal processing applications, video de-/encoding, image processing, or a combination of these tasks. For this purpose, the HiBRID-SoC integrates three fully programmable processors cores and various interfaces onto a single chip, all tied to a 64-Bit AMBA AHB bus. The processor cores are individually optimized to the particular computational characteristics of different application fields, complementing each other to deliver high performance levels with high flexibility at reduced system cost. The HiBRID-SoC is fabricated in a 0.18 μm 6LM standard-cell CMOS technology, occupies about 81 mm2, and operates at 145 MHz. An MPEG-4 Advanced Simple Profile decoder in full D1 resolution requires about 120 MHz for real-time operation on the HiBRID-SoC, utilizing only two of the three cores. Together with the third core, a custom region-of-interest (ROI) based surveillance application can be built.
- Organisation(s)
-
Institute of Microelectronic Systems
- Type
- Article
- Journal
- Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology
- Volume
- 41
- Pages
- 9-20
- No. of pages
- 12
- ISSN
- 1387-5485
- Publication date
- 01.08.2005
- Publication status
- Published
- Peer reviewed
- Yes
- ASJC Scopus subject areas
- Signal Processing, Information Systems, Electrical and Electronic Engineering
- Electronic version(s)
-
https://doi.org/10.1007/s11265-005-6247-1 (Access:
Closed)
