A modular coprocessor architecture for embedded real-time image and video signal processing

authored by

Holger Flatt, Sebastian Hesselbarth, Sebastian Flügel, Peter Pirsch

Abstract

This paper presents a modular coprocessor architecture for embedded real-time image and video signal processing. Applications are separated into high-level and low-level algorithms and mapped onto a RISC and a coprocessor, respectively. The coprocessor comprises an optimized system bus, different application specific processing elements and I/O interfaces. For low volume production or prototyping, the architecture can be mapped onto FPGAs, which allows flexible extension or adaption of the architecture. Depending on the complexity of the coprocessor data paths, frequencies up to 150 MHz have been achieved on a Virtex II-Pro FPGA. Compared to a RISC processor, the performance gain for an SSD algorithm is more than factor 70.

Organisation(s)

Institute of Microelectronic Systems

Type

Conference contribution

Pages

241-250

No. of pages

10

Publication date

2007

Publication status

Published

Peer reviewed

Yes

ASJC Scopus subject areas

Theoretical Computer Science, General Computer Science

Electronic version(s)

https://doi.org/10.1007/978-3-540-73625-7_26 (Access: Open)