SmartHeaP

A High-level Programmable, Low Power, and Mixed-Signal Hearing Aid SoC in 22nm FD-SOI

authored by

Jens Christian Karrenbauer, Simon Christian Klein, Sven Johannes Schönewald, Lukas Konrad Gerlach, Meinolf Blawat, Jens Benndorf, Holger Christoph Blume

Abstract

To handle the advances in hearing aid algorithms, the need for high-level programmable but low-power hardware architectures arises. Therefore, this paper presents the Smart Hearing Aid Processor (SmartHeaP), a mixed-signal system on chip (SoC) fabricated in 22 nm fully-depleted silicon-on-insulator (FD-SOI) with an adaptive body biasing (ABB) unit and a total die size of 7.36 mm² . The proposed SoC consists of two application-specific instruction set processor (ASIP) architectures: firstly, a Cadence Tensilica Fusion G6 instruction set architecture, extended with custom instructions for audio processing, and secondly, a Cadence Tensilica LX7 for wireless interfacing, e.g., Bluetooth Low Energy. Furthermore, an analog front-end and digital audio interfaces are added. The large local memory of 2 MB and a high-level software environment enables memory-intensive algorithms to be deployed quickly. Typical hearing aid algorithms in a real-time setup are used to evaluate the power consumption of the SoC at different operating frequencies. At 50 MHz, a mean power consumption of less than 2.2 mW was measured, resulting in an efficiency of 34.8 µW/MHz.

Organisation(s)

Architectures and Systems Section

External Organisation(s)

Dream Chip Technologies GmbH

Type

Conference contribution

Pages

265-268

No. of pages

4

Publication date

2022

Publication status

Published

Peer reviewed

Yes

ASJC Scopus subject areas

Hardware and Architecture, Electrical and Electronic Engineering, Electronic, Optical and Magnetic Materials, Instrumentation, Artificial Intelligence

Electronic version(s)

https://doi.org/10.1109/ESSCIRC55480.2022.9911325 (Access: Closed)