RAPANUI

Rapid prototyping for media processor architecture exploration

authored by: Guillermo Payá Vayá, Javier Martín Langerwerf, Peter Pirsch
Abstract: This paper describes a new rapid prototyping-based design framework for exploring and validating complex multiprocessor architectures for multimedia applications. The new methodology combines a typical ASIC flow with an FPGA flow focused on rapid prototyping. In order to make an exhaustive verification of the system architecture, a reference model that specifies the hardware implementation is used for validating both, HDL description and emulated system. Functional coverage in addition to traditional code coverage is used to test 100% of data, control and structural hazards of the system architecture. The reference model is also part of a stand-alone simulation environment. This allows hardware and application development be supported by a unique system model.
Organisation(s): Institute of Microelectronic Systems
Type: Conference article
Journal: Lecture Notes in Computer Science
Volume: 3553
Pages: 32-40
No. of pages: 9
ISSN: 0302-9743
Publication date: 2005
Publication status: Published
Peer reviewed: Yes
ASJC Scopus subject areas: Theoretical Computer Science, General Computer Science
Electronic version(s): https://doi.org/10.1007/11512622_5 (Access: Closed)