3-D placement considering vertical interconnects

authored by

I. Kaya, M. Olbrich, E. Barke

Abstract

3D integration is going to play an important role in the future. Increasing complexity and increasing impact of interconnects to integrated circuit (IC) performance makes 3D more and more attractive. EDA tools for 3D design hardly exist. We propose a new 3D standard-cell placer based on quadratic programming. It ensures a reduction of the total wirelength and can deal with standard cells and vertical interconnects simultaneously. The final result is a legalized, design rule compliant and discrete 3D placement.

Organisation(s)

Institute of Microelectronic Systems

Type

Conference contribution

Pages

257-258

No. of pages

2

Publication date

2003

Publication status

Published

Peer reviewed

Yes

ASJC Scopus subject areas

Hardware and Architecture, Electrical and Electronic Engineering

Electronic version(s)

https://doi.org/10.1109/SOC.2003.1241509 (Access: Unknown)