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A runtime-configurable emulation-based stochastic timing analysis framework

authored by: Moritz Weißbrich, Lukas Gerlach, Holger Blume, A. Najafi, A. García-Ortiz, Guillermo Payá-Vayá
Abstract: ASICs for Stochastic Computing conditions are designed for higher energy-efficiency or performance by sacrificing computational accuracy due to intentional circuit timing violations. To optimize the stochastic behavior, iterative timing analysis campaigns have to be carried out for a variety of circuit timing corner cases. However, the application of common event-driven logic simulators usually leads to excessive analysis runtimes, increasing design time for hardware developers. In this paper, a gate-level netlist-oriented FPGA-based timing analysis framework is proposed, offering a runtime-configuration mechanism for emulating different timing corner cases in hardware without requiring multiple FPGA bitstreams. Logic gates are instrumented with a quantization-based delay model and a critical path selection algorithm is used to reduce the FPGA resource overhead. For an exemplary design space exploration of stochastic CORDIC units, speed-up factors of up to 48 for 10 ps or 476 for 100 ps timing quantization are achieved while maintaining timing behavior deviations lower than 1.5% or 4% to timing simulations, respectively.
Organisation(s): Institute of Microelectronic Systems
External Organisation(s): University of Bremen
Type: Article
Journal: INTEGRATION
Volume: 69
Pages: 120-137
No. of pages: 18
ISSN: 0167-9260
Publication date: 11.2019
Publication status: Published
Peer reviewed: Yes
ASJC Scopus subject areas: Software, Hardware and Architecture, Electrical and Electronic Engineering
Sustainable Development Goals: SDG 7 - Affordable and Clean Energy
Electronic version(s): https://doi.org/10.1016/j.vlsi.2019.01.002 (Access: Closed)