Multicore system-on-chip architecture for MPEG-4 streaming video

authored by

Mladen Bereković, Hans Joachim Stolberg, Peter Pirsch

Abstract

The newly defined MPEG-4 Advanced Simple (AS) profile delivers single-layered streaming video in digital television (DTV) quality in the promising 1-2 Mbit/s range. However, the coding tools involved add significantly to the complexity of the decoding process, raising the need for further hardware acceleration. A programmable multicore system-on-chip (SOC) architecture is presented which targets MPEG-4 AS profile decoding of ITU-R 601 resolution streaming video. Based on a detailed analysis of corresponding bitstream statistics, the implementation of an optimized software video decoder for the proposed architecture is described. Results show that overall performance is sufficient for real-time AS profile decoding of ITU-R 601 resolution video.

Organisation(s)

Institute of Microelectronic Systems

External Organisation(s)

Institute of Electrical and Electronics Engineers (IEEE)

Type

Article

Journal

IEEE Transactions on Circuits and Systems for Video Technology

Volume

12

Pages

688-699

No. of pages

12

ISSN

1051-8215

Publication date

08.2002

Publication status

Published

Peer reviewed

Yes

ASJC Scopus subject areas

Media Technology, Electrical and Electronic Engineering

Electronic version(s)

https://doi.org/10.1109/TCSVT.2002.800860 (Access: Closed)