Thermal analysis of the design parameters of a QFN package soldered on a PCB using a simulation approach

authored by: K. Hollstein, X. Yang, K. Weide-Zaage
Abstract: Quad-Flat-No-Lead (QFN) packages are electric components that are producing a substantial amount of heat during operation due to significant power loss. Resulting elevated temperatures can lead to critical damage of the chip and the package, which could cause a loss of functionality. Therefore, controlling the maximum temperature within the package is crucial. Using thermal vias embedded in the PCB underneath the QFN is a common concept to support the heat flow. In this paper a simulation approach is presented using 3D Finite-Element-Modelling to identify the impact of influencing parameters on the temperature distribution within the package. Therefore, the build-up of the model is explained and applied material properties are given. Results for the determined temperature distribution for a reference parameter set are presented. Geometrical parameters like the thickness and the area size of the thermal pads and the copper layers are varied. Furthermore, the via count and distribution has been changed and additional inner layers have been added in order to act as a heat sink. The impact of these variations on the resulting component temperature will be discussed in the analysis part. The paper will round up with a discussion of simulation results and an outlook for future work.
Organisation(s): Institute of Microelectronic Systems
Type: Article
Journal: Microelectronics reliability
Volume: 120
ISSN: 0026-2714
Publication date: 05.2021
Publication status: Published
Peer reviewed: Yes
ASJC Scopus subject areas: Electronic, Optical and Magnetic Materials, Atomic and Molecular Physics, and Optics, Condensed Matter Physics, Safety, Risk, Reliability and Quality, Surfaces, Coatings and Films, Electrical and Electronic Engineering
Electronic version(s): https://doi.org/10.1016/j.microrel.2021.114118 (Access: Closed)