Three-dimensional voids simulation in chip metallization structures

A contribution to reliability evaluation

authored by

D. Dalleau, K. Weide-Zaage

Abstract

The understanding of metal migration mechanisms remains today a big interest. Metallization structures are getting more and more smaller whereas the reliability of integrated circuits needs to be improved. The increasing capacities of numerical analysis and simulation tools like the Finite Element Method (FEM) allow the prediction of failure location degradation caused by this phenomena. In this paper, an algorithm for 3-D simulation of void formation in metallizations is presented, taking into account the electromigration, as well as the thermomigration and the stressmigration contributions. Two typical structures like a meander- and a pad structure are investigated. The void evolution inside the metallization structure, as well as the change of the electrical resistivity of the interconnect are simulated. A new method for the time-dependent calculation of the phenomena is also proposed, and an evaluation of the Time-To-Failure (TTF) for the investigated structures is presented. The results obtained by simulation are found in good agreement with SEM observations.

Organisation(s)

Laboratorium f. Informationstechnologie

Type

Article

Journal

Microelectronics reliability

Volume

41

Pages

1625-1630

No. of pages

6

ISSN

0026-2714

Publication date

09.2001

Publication status

Published

Peer reviewed

Yes

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials, Atomic and Molecular Physics, and Optics, Safety, Risk, Reliability and Quality, Condensed Matter Physics, Surfaces, Coatings and Films, Electrical and Electronic Engineering

Electronic version(s)

https://doi.org/10.1016/S0026-2714(01)00151-2 (Access: Unknown)