Degradation behavior in upstream/downstream via test structures

authored by

J. Kludt, K. Weide-Zaage, M. Ackermann, V. Hein, C. Kovács

Abstract

The miniaturization process of CMOS components creates new challenges for the development of integrated circuits. Especially the connections with a tungsten via between two metal layers can be a problem. Changes in geometry can bear on reliability problems. For a robust metallization design it is necessary to know, how strong the influence of the tungsten via alignment affects the physical behavior. The lifetime of up- and downstream test structures with different overlaps as well as strong misalignment was determined by measurements. Investigations have shown that the alignments have a noticeable effect on the reliability and performance of test structures. The downstream line shows the expected lifetime behavior. For the upstream line no influence of the misalignment on the lifetime was found. Simulations are taken into account to understand the thermal-electrical and mechanical behavior.

Organisation(s)

Laboratorium f. Informationstechnologie

External Organisation(s)

X-FAB Silicon Foundries SE

Type

Article

Journal

Microelectronics reliability

Volume

54

Pages

1724-1728

No. of pages

5

ISSN

0026-2714

Publication date

01.09.2014

Publication status

Published

Peer reviewed

Yes

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials, Atomic and Molecular Physics, and Optics, Safety, Risk, Reliability and Quality, Condensed Matter Physics, Surfaces, Coatings and Films, Electrical and Electronic Engineering

Electronic version(s)

https://doi.org/10.1016/j.microrel.2014.07.042 (Access: Closed)