Cross-Layer Fault-Space Pruning for Hardware-Assisted Fault Injection

authored by

Christian Dietrich, Achim Schmider, Oskar Pusz, Guillermo Payá Vayá, Daniel Lohmann

Abstract

With shrinking structure sizes, soft-error mitigation has become a major challenge in the design and certification of safety-critical embedded systems. Their robustness is quantified by extensive faultinjection campaigns, which on hardware level can nevertheless cover only a tiny part of the fault space. We suggest Fault-Masking Terms (MATEs) to effectively prune the fault space for gate-level fault injection campaigns by using the (software-induced) hardware state to dynamically cut off benign faults. Our tool applied to an AVR core and a size-optimized MSP430 implementation shows that up to 21 percent of all SEUs on flip-flop level are masked within one clock cycle.

Organisation(s)

Systems and Computer Architecture Section
Architectures and Systems Section

Type

Conference contribution

Publication date

06.2018

Publication status

Published

Peer reviewed

Yes

ASJC Scopus subject areas

Computer Science Applications, Control and Systems Engineering, Electrical and Electronic Engineering, Modelling and Simulation

Electronic version(s)

https://doi.org/10.1145/3195970.3196019 (Access: Closed)
https://doi.org/10.1109/DAC.2018.8465787 (Access: Closed)