Reliability of wafer level chip scale packages

authored by

R. Rongen, R. Roucou, P. J. Vd Wel, F. Voogt, F. Swartjes, K. Weide-Zaage

Abstract

This paper describes applied reliability for semiconductor components in Wafer Level Chip Scale Packages (CSP). To develop and qualify reliable products, the failure mechanism driven approach is to be followed instead of the stress test driven one. This will be explained by elaborating on two failure mode cases assessed in WL-CSP: cracks in the passivation layer and top metal of the die/silicon and electromigration in the solder joints. A new TMCL test method is described that covers the direct (thermo) mechanical interaction between PCB and the die/design via the solder joint. In addition, the relevance of Finite Element Modeling to understand the origin of failure modes is shown which allows for optimizing designs and materials. Finally, the concept of life time prediction, starting from application use descriptions and mission profiles, is introduced. Reliability testing, modeling and life time prediction/reliability statistics are combined in one framework to accommodate for the creation of application specific, highly reliable components.

Organisation(s)

Laboratorium f. Informationstechnologie

External Organisation(s)

NXP Semiconductors N.V.

Type

Article

Journal

Microelectronics reliability

Volume

54

Pages

1988-1994

No. of pages

7

ISSN

0026-2714

Publication date

01.09.2014

Publication status

Published

Peer reviewed

Yes

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials, Atomic and Molecular Physics, and Optics, Safety, Risk, Reliability and Quality, Condensed Matter Physics, Surfaces, Coatings and Films, Electrical and Electronic Engineering

Electronic version(s)

https://doi.org/10.1016/j.microrel.2014.07.012 (Access: Closed)