A DAC Sharing and Linearization Technique for Time-Interleaved Incremental Delta-Sigma ADCs

authored by

Jesko Flemming, Bernhard Wicht, Pascal Witte

Abstract

This paper presents a digital-to-analog converter (DAC) sharing method for time-interleaved (TI)-incremental delta-sigma modulators (I-ΔΣMs), which allows significant savings of passives by 40 % in the DACs. The proposed DAC sharing shows an increased robustness to nonlinearities and is further adapted to a linearization technique known from non-TI-I-ΔΣMs. The paper extends the known linearization technique to achieve optimal signal to noise and distortion ratio (SNDR) across the modulator's entire dynamic range (DR). An increase of 7 dB in SNDR is demonstrated for low input signals powers, which has not been shown before. It is demonstrated, that the high linearity of the system allows to compensate for the gain mismatch in TI operation with a simple gain factor to retain near ideal performance. Furthermore, the paper proposes a practical circuit implementation for the shared DAC and a correlation based error estimation to determine the channel gain mismatch.

Organisation(s)

Institute of Microelectronic Systems

External Organisation(s)

University of Applied Sciences and Arts Hannover (HsH)

Type

Conference contribution

No. of pages

5

Publication date

2024

Publication status

Published

Peer reviewed

Yes

ASJC Scopus subject areas

Electrical and Electronic Engineering

Electronic version(s)

https://doi.org/10.1109/ISCAS58744.2024.10557987 (Access: Closed)