On the design of scalable massively parallel CRC circuits
- authored by
- Konstantin Septinus, Thuyen Le, Ulrich Mayer, Peter Pirsch
- Abstract
This paper presents a scalable massively parallel CRC architecture for high-speed network processing. The proposed method considers wide data busses, which result in highest throughput. In addition, data streams are processed without interrupts. An investigated 65nm-ASIC implementation example for 32-bit CRC encoding operates on 58 GBps data streams at reasonable costs (0.036 mm 2). The proposed method can be exploited furthermore in order to develop a configurable circuit for a group of generator polynomials, without the requirement of fully programmable architecture.
- Organisation(s)
-
Institute of Microelectronic Systems
- External Organisation(s)
-
IBM
- Type
- Conference contribution
- Pages
- 142-145
- No. of pages
- 4
- Publication date
- 2007
- Publication status
- Published
- Peer reviewed
- Yes
- ASJC Scopus subject areas
- General Engineering
- Electronic version(s)
-
https://doi.org/10.1109/ICECS.2007.4510950 (Access:
Closed)
