A Novel Chaining-Based Indirect Addressing Mode in a Vertical Vector Processor

authored by

Sven Gesper, Daniel Köhler, Gia Bao Thieu, Jasper Homann, Frank Meinl, Holger Blume, Guillermo Payá-Vayá

Abstract

Efficient processing architectures for irregular data patterns require vector element addressing with flexible indices. Therefore, state-of-the-art SIMD vector extensions implement gather and scatter instructions for indexed addressing of data in memory. In vertical vector processors, different data is processed sequentially in parallel lanes and can be exchanged via chaining. This paper proposes an extension of such chaining mechanisms in a vertical vector processor architecture (V2PRO) to flexibly chain not only data but also address offsets between vector lanes. The indirect addressing enables vector access patterns with irregular strides for both register file and memory. The extension has a low hardware overhead of +4.8 % lookup tables and +1.8% registers on a Xilinx Ultrascale+ FPGA. A runtime evaluation for two applications from computer vision, namely Deformable Convolutions and point cloud encoding with PointPillars, demonstrates speedups of at least an order of magnitude with the proposed extension.

Organisation(s)

Institute of Microelectronic Systems

External Organisation(s)

Technische Universität Braunschweig
Robert Bosch GmbH

Type

Conference contribution

Pages

167-182

No. of pages

16

Publication date

28.01.2025

Publication status

Published

Peer reviewed

Yes

ASJC Scopus subject areas

Theoretical Computer Science, General Computer Science

Electronic version(s)

https://doi.org/10.1007/978-3-031-78377-7_12 (Access: Closed)