KAVUAKA

A Low Power Application Specific Hearing Aid Processor

authored by

Lukas Gerlach, Guillermo Paya-Vaya, Holger Blume

Abstract

The integration of application specific instruction set processors (ASIPs) in hearing aids requires various architectural customizations and software-side optimizations in order to meet the stringent power consumption constraints and processing performance demands. This paper presents the KAVUAKA application specific hearing aid processor and its ASIC integration as a system on chip (SoC). The final system contains four KAVUAKA processor cores and ten co-processors. Each of these processors and co-processors were individually customized and differ in their data path width. The processors are organized in two clusters, which share memories, an audio interface, co-processors and a serial interface. With this system, different hearing aid systems are evaluated in terms of performance, power and area by activating different processor and co-processor combinations. A 40 nm low power technology was used to build this research hearing aid system. The die size is 3.6 mm 2 with less than 1 mm 2 per core. The measured average power consumption is less than 1 mW per core.

Organisation(s)

Institute of Microelectronic Systems

Type

Conference contribution

Pages

99-104

No. of pages

6

Publication date

10.2019

Publication status

Published

Peer reviewed

Yes

ASJC Scopus subject areas

Hardware and Architecture, Software, Electrical and Electronic Engineering

Sustainable Development Goals

SDG 3 - Good Health and Well-being

Electronic version(s)

https://doi.org/10.1109/VLSI-SoC.2019.8920354 (Access: Closed)