Overlap design for higher tungsten via robustness in AlCu metallizations

authored by

Jorg Kludt, Kirsten Weide-Zaage, Markus Ackermann, Verena Hein

Abstract

Due to the miniaturization process of the CMOS components metallization structures are becoming more and more complex. Better knowledge to improve via robustness for high current applications is needed. Geometry changes can have a big effect on the physical behaviour. For higher robust metallization systems it is necessary to learn more about overlap design to meet the most economic layout. Slotted high current line layouts do not allow the use of big via areas. Furthermore the number of vias increases the resistance. Investigations have shown the existence of an optimal overlap.

Organisation(s)

Laboratorium f. Informationstechnologie

External Organisation(s)

X-FAB Silicon Foundries SE

Type

Conference contribution

Pages

137-141

No. of pages

5

Publication date

2013

Publication status

Published

Peer reviewed

Yes

ASJC Scopus subject areas

Electrical and Electronic Engineering, Safety, Risk, Reliability and Quality, Electronic, Optical and Magnetic Materials

Electronic version(s)

https://doi.org/10.1109/IIRW.2013.6804178 (Access: Unknown)